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Persistent Snapshot Isolation with Unlimited Reads on Commodity Hardware Transactional Memory
DescriptionPersistent Memory (PM) has been proposed and commercially used as a novel generation of storage devices capable of competing with both primary and secondary memory, attaining features such as data persistency and byte addressability.
These devices paved the way for researchers to develop Transactional Memories (TMs) that, besides providing atomic transactions in main memory, because this memory can also be persistent, also deliver durable transactions. Unfortunately, combining PM and TM is challenging, as the most efficient implementations of TM, i.e., Hardware Transaction Memories (HTMs), operate at the level of volatile CPU caches.
We present our early-stage work on PSI, the first durable Persistent Hardware Transaction Memory for IBM's POWER systems. Our work builds on SI-HTM, which is a volatile HTM solution, and expands it with durability. We show that PSI imposes a relatively low overhead of 23% when compared with a volatile solution.
These devices paved the way for researchers to develop Transactional Memories (TMs) that, besides providing atomic transactions in main memory, because this memory can also be persistent, also deliver durable transactions. Unfortunately, combining PM and TM is challenging, as the most efficient implementations of TM, i.e., Hardware Transaction Memories (HTMs), operate at the level of volatile CPU caches.
We present our early-stage work on PSI, the first durable Persistent Hardware Transaction Memory for IBM's POWER systems. Our work builds on SI-HTM, which is a volatile HTM solution, and expands it with durability. We show that PSI imposes a relatively low overhead of 23% when compared with a volatile solution.
Author/Presenters
Event Type
Workshop
TimeFriday, 17 November 20239:30am - 10am MST
Location405-406-407
Data Movement and Memory
Fault Handling and Tolerance
Heterogeneous Computing
Security
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