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Comparative Evaluation of Bandwidth-Bound Applications on the Intel Xeon CPU MAX Series
DescriptionWe explore the performance of Intel Xeon MAX CPU Series, representing the most significant new variation upon the classical CPU architecture since the Xeon Phi. Given a large on-package high-bandwidth memory, the bandwidth-to-compute ratio has significantly shifted compared to other CPUs on the market. Since a large fraction of HPC workloads are sensitive to the available bandwidth, we explore how this architecture performs on a selection of HPC proxies and applications that are mostly sensitive to bandwidth, and how it compares to the previous 3rd generation Xeon processors (Ice Lake) and an EPYC 7003 Series Processor with 3D V-Cache Technology. We explore performance with different parallel implementations (MPI, MPI+OpenMP, MPI+SYCL), compiled with different compilers and flags, and executed with or without hyperthreading. We show how performance bottlenecks are shifted from bandwidth to communication latencies for some applications, and demonstrate speedups compared to the previous generation between 2.0x-4.3x.
Event Type
Workshop
TimeMonday, 13 November 20239:30am - 10am MST
Location503-504
Modeling and Simulation
Performance Measurement, Modeling, and Tools
W