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Prototype of a Batched Quantum Circuit Simulator for the Vector Engine
DescriptionState-of-the-art quantum circuit simulators have mostly focused on scaling the number of qubits. However, we argue that studying current noisy quantum computers and variational quantum algorithms benefits from high-throughput simulation of intermediate-scale quantum circuits. We present the first implementation and evaluation of a batched quantum simulator on the NEC Vector Engine (VE), a vector processor with massive memory bandwidth ideal for memory-intensive state vector simulation. To take advantage of the long-vector architecture of VE, we design a parallelization strategy and memory layout suited for batched state vector simulation. Our preliminary evaluation shows that the performance of our simulator on VE Type 20B outperforms a dual-socket CPU system by 12x. Furthermore, the performance of VE is identical to that of cuStateVec on A100 40 GB, matching the peak bandwidth of the two processors. This suggests the latest VE with higher memory bandwidth is expected to outperform A100.
Event Type
Workshop
TimeMonday, 13 November 20239:20am - 9:40am MST
Location603
Quantum Computing
Software Engineering
W