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Characterizing the Performance of Triangle Counting on Graphcore's IPU Architecture

SessionTenth Workshop on Accelerator Programming and Directives (WACCPD 2023)

DescriptionIn recent years, we have seen an emergence of novel spatial architectures to accelerate domain-specific workloads like Machine Learning. There is a need to investigate their performance characteristics for traditional HPC workloads for their tighter integration with current and future heterogeneous compute resources. In this work, we implement, optimize and evaluate a parallel algorithm for Triangle Counting for graphs in Bulk Synchronous Parallel (BSP) model for Graphcore’s IPU architecture as well as discuss lessons learned. This study demonstrates IPU's competency in handling such irregular workloads by providing an average speedup of up to 5.3x over NVIDIA A100 GPU on real-world datasets.

Author/Presenters

Reet Barik

Argonne National Laboratory (ANL)

Washington State University