Author

Mr. Gervasi has over 45 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi became a memory specialist for companies including S3, Transmeta, Netlist, SimpleTech, and Nantero, and is now Principal Systems Architect for Wolley, developing CXL based memory solutions.

Mr. Gervasi been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and memory modules during the development of DDR1 through DDR6. He is currently the chairman of the JEDEC Alternative Memory committee. He received the JEDEC Technical Excellence award, their highest honor, in 2020.