Author

Craig Warner is currently the prototype architect in Micron’s Scalable Memory Systems path finding group. He has over 30 years expertise in design and post-silicon validation of ASIC and FPGA designs. Many of his designs are core electronic components for Hewlett Packard Enterprise servers. His technical areas of expertise include IO architectures, cache coherency protocols, RISC-V processor architectures, and on-die interconnection networks. Craig received his MS in Computer Engineering from Purdue University and his BS in Computer Engineering from Iowa State University.