Presentation
SIGN IN TO VIEW THIS PRESENTATION Sign In
Invited Talk: Scaling Computing for Concurrent Data Structures Using Near-Memory Processing Architectures
DescriptionIn recent years, there has been a renewed interest in near-memory processing (NMP) architectures as a workaround for the performance and energy issues of frequent and irregular memory accesses. However, effective use of NMP architectures requires rethinking data structures and their algorithms, especially as these data structures scale up in size well beyond the size of last level caches. In this talk, I will focus on cache-optimized data structures, such as skiplists and B+ trees, often used in online transaction processing (OLTP) systems to enable fast key-based lookups. I will present a hardware/software co-design solution of NMP-aware algorithms for these concurrent data structures and show that our approach can improve performance by more than 2X compared to the state-of-the-art.
Presenter
Event Type
Workshop
TimeSunday, 12 November 20239am - 9:40am MST
Location505
Accelerators
Edge Computing
Heterogeneous Computing
W