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Streaming Hardware Compressor Generator Framework

SessionThe 9th International Workshop on Data Analysis and Reduction for Big Scientific Data (DRBSD-9)

DescriptionThe interest in and strong demand for application-specific accelerators in computing and sensor data processing are rising. Simultaneously, data movement bottlenecks are increasingly becoming a significant limiting factor for these accelerators. Integrating an extremely resource-efficient, ultra-low-latency compressor block into their data path or pipeline could solve or mitigate data movement bottlenecks and enhance the performance of these accelerators. However, workflows for hardware compressor architecture exploration are little studied. We introduce a generator framework for designing, verifying, and estimating resources in streaming hardware compressor architectures to fill the gap. This framework assists users in exploring different compressor architectures with different compressor building blocks, evaluating their characteristics (latency, throughput, gate counts), and generating RTL code for integrating them into custom accelerator designs. Our motivation is to bridge the gap between software and hardware experts through this proposed framework as a co-design tool.

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