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Enabling Communication with FPGA-Based Network-Attached Accelerators for HPC Workloads
SessionNinth International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC 2023)
DescriptionThe use of stand-alone, network-coupled FPGA accelerators is intended to significantly increase the energy efficiency of HPC applications and thus also of HPC data centers. A loose coupling between the nodes of the HPC data center and the FPGAs is established through the high-speed network of the data center. This allows greater flexibility in combining different nodes and accelerators. Both the resulting energy savings and the increased flexibility through the network connection, enable the economical use of FPGAs. This work presents a communication stack to integrate the so-called Network-attached Accelerator (NAA) into the HPC data center. A low-level RDMA API and a high-level Remote Procedure Call API is designed on top of the RoCEv2 communication stack. The experimental results over 100 Gbps RoCEv2 show that our design and implementation deliver performance close to the theoretical maximum.
Author/Presenters
Event Type
Workshop
TimeFriday, 17 November 20239:40am - 10am MST
Location403-404
Architecture and Networks
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