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Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs
SessionNinth International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC 2023)
DescriptionIn this work, we introduce Altis-SYCL, a benchmark suite based on SYCL for GPUs and FPGAs. For developing Altis-SYCL, we leverage the oneAPI heterogeneous programming framework in two consecutive steps: 1) by using the modern Altis GPGPU benchmark suite as baseline and migrating it from CUDA to SYCL, and 2) by exploring several techniques to optimize the performance of the resulting SYCL code. Our migration-and-optimization methodology starts targeting GPUs and progressively moves towards FPGAs. In this process, we discuss the differences between device-specific strategies as well as detailing the required code refactoring and optimization efforts. The performance of Altis-SYCL was evaluated on Stratix 10 and Agilex FPGAs, and for some applications, their execution runtimes were competitive with those achieved on latest high-end GPUs. The corresponding code is released as open source
under: https://github.com/esa-tu-darmstadt/altis_sycl.
under: https://github.com/esa-tu-darmstadt/altis_sycl.
Event Type
Workshop
TimeFriday, 17 November 202310:50am - 11:10am MST
Location403-404
Architecture and Networks
W