Presentation
SIGN IN TO VIEW THIS PRESENTATION Sign In
Stencil-HMLS: A Multi-Layered Approach to the Automatic Optimization of Stencil Codes on FPGA
SessionNinth International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC 2023)
DescriptionThe challenges associated with effectively programming FPGAs have been a major blocker in popularizing reconfigurable architectures for HPC workloads. However new compiler technologies, such as MLIR, are providing new capabilities which potentially deliver the ability to extract domain specific information and drive automatic structuring of codes for FPGAs.
We explore domain specific optimizations for stencils, a fundamental access pattern in scientific computing, to obtain high performance on FPGAs via automated code structuring. We propose Stencil-HMLS, a multi-layered approach to automatic optimization of stencil codes and introduce the HLS dialect, which brings FPGA programming into the MLIR ecosystem. Using the PSyclone Fortran DSL, we demonstrate an improvement of 14-100 times with respect to the next best performant state-of-the-art tool. Furthermore, our approach is 14-92 times more energy efficient than the next most energy efficient approach.
We explore domain specific optimizations for stencils, a fundamental access pattern in scientific computing, to obtain high performance on FPGAs via automated code structuring. We propose Stencil-HMLS, a multi-layered approach to automatic optimization of stencil codes and introduce the HLS dialect, which brings FPGA programming into the MLIR ecosystem. Using the PSyclone Fortran DSL, we demonstrate an improvement of 14-100 times with respect to the next best performant state-of-the-art tool. Furthermore, our approach is 14-92 times more energy efficient than the next most energy efficient approach.
Author/Presenters
Event Type
Workshop
TimeFriday, 17 November 202311:30am - 11:50am MST
Location403-404
Architecture and Networks
W