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MSR-genie: Navigating Model Specific Registers across Processor Generations
DescriptionPerformance tuning of High-Performance Computing (HPC) applications depends on sophisticated tuning of parameters on diverse architectures. These parameters are made available by vendors through low-level dials such as Model-Specific Registers (MSRs). While the MSRs themselves provide a powerful mechanism for users to monitor and control processor features, accessing them is laborious due to lack of standard interfaces and clear documentation. As a result, the burden of determining which MSRs to consider and how to fine-tune them for an application lies on the end user.
We present MSR-genie, an efficient and extensible query tool which reduces this user-level burden and allows them to query bidirectionally across MSR lists as well as a processor families and models, and providing them with guidance on appropriate bitmasks. The MSR-genie tool is open-source and easily extensible, and we demonstrate its effectiveness with over thirty Intel processor models and over two-thousand unique MSRs.
We present MSR-genie, an efficient and extensible query tool which reduces this user-level burden and allows them to query bidirectionally across MSR lists as well as a processor families and models, and providing them with guidance on appropriate bitmasks. The MSR-genie tool is open-source and easily extensible, and we demonstrate its effectiveness with over thirty Intel processor models and over two-thousand unique MSRs.
Author/Presenters
Event Type
Workshop
TimeSunday, 12 November 202311:38am - 11:58am MST
Location605
Programming Frameworks and System Software
W