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A New Sparse GEneral Matrix-Matrix Multiplication Method for Long Vector Architecture by Hierarchical Row Merging
DescriptionVector processors have become essential to high-performance computing in scientific and engineering applications, especially in numerical calculations that leverage data parallelism. With escalating computational demands, the efficient execution of Sparse GEneral Matrix-matrix Multiplication (SpGEMM) on vector processors has become crucial. However, it brings challenges for vector processors due to its complex data structures and irregular memory access patterns.
We present a new method designed to perform SpGEMM on vector processors, inspired by Iterative Row Merging. The proposed method hierarchically merges rows by utilizing long vector instructions. We evaluate the proposed method against other methods across 27 sparse matrices. The results indicate that the proposed method outperforms other methods for 22 out of the 27 sparse matrices, reaching up to 31.9 times better performance in the best case. Furthermore, we compare with the GPU implementation that inspired our proposed method, using the same generation of GPUs.
We present a new method designed to perform SpGEMM on vector processors, inspired by Iterative Row Merging. The proposed method hierarchically merges rows by utilizing long vector instructions. We evaluate the proposed method against other methods across 27 sparse matrices. The results indicate that the proposed method outperforms other methods for 22 out of the 27 sparse matrices, reaching up to 31.9 times better performance in the best case. Furthermore, we compare with the GPU implementation that inspired our proposed method, using the same generation of GPUs.
Event Type
Workshop
TimeSunday, 12 November 20232:50pm - 3pm MST
Location702
Algorithms
Applications
Architecture and Networks
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