Author

Dr. Cesarini graduated in Computer Engineering from the University of Bologna (Italy) in 2014, where he also earned his Ph.D. in Electronics, Telecommunications, and Information Technologies Engineering in 2019. He is currently an HPC Specialist at Cineca’s HPC department where he works in the area of performance optimization and evaluation of next-generation HPC architectures to design the roadmap of CINECA’s HPC infrastructures. He is a member of the Research and Innovation Advisory Group (RIAG) of the EuroHPC Joint Undertaking (EuroHPC JU), and he represents Cineca in the Steering Board of the European Technology Platform for HPC (ETP4HPC). He manages for Cineca several research projects funded by Horizon Europe and EuroHPC JU like the European Processor Initiative (EPI-SGA1 and EPI-SGA2), the advanced pilots towards the European supercomputers (EUPEX), and the Resource Management for the Exascale Era (REGALE).