Author

Josef Weidendorfer is a lecturer for computer science at the Technical University of Munich (TUM). He works at the Leibniz Computing Centre (LRZ) as senior HPC scientist on smooth migration strategies to future systems. Research interests include performance analysis and tuning, parallel programming models, and heterogeneous computing. Before, he was senior researcher and teaching assistant at TUM. His habilitation at TUM in 2016 proposed simulation-driven performance analysis with a focus on the memory hierarchy. He received his Ph.D. from TUM in 2003, studying load balancing issues in car crash simulation on industrial code at BMW AG.