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NVMe Over CXL (NVMe-oC): An Ultimate Optimization of Host-Device Data Movement
SessionExhibitor Forum: Machines II
DescriptionCompute Express Link (CXL), introduced in 2019, manages the Host-Accelerator coherency and the Host-Memory interface. CXL fabric further enables the disaggregated memory architecture. Most of the CXL developments are on the memory interface and not on the storage interface. In this paper, Wolley evaluates the impact of CXL to the storage interface.
NVMe protocol moves the data in a block form from a Device to a Host memory utilizing the PCIe as the transport. There are several attempts to minimize such Host-Device data movement which is an important factor of performance bottleneck and power consumption. One such effort is Computational Storage that moves the compute from the Host to the Device, and the Device only sends the computed result back to the Host at a much lower data rate.
Wolley proposes using NVMe over CXL (NVMeoC) to optimize the Host-Device data movement. In most applications, the Host only accesses a small portion of the entire block data retrieved from the Device. With NVMeoC, the Device keeps a CXL staging area that is managed as a part of the Host memory. Once the block data is moved to the CXL staging memory through NVMe operation, the actual Host-Device data movement using CXL.mem is just a fraction of the total block data. Wolley will compare in details of the latency and the power consumption between the NVMe over PCIe and NVMe over CXL in several different of applications.
NVMe protocol moves the data in a block form from a Device to a Host memory utilizing the PCIe as the transport. There are several attempts to minimize such Host-Device data movement which is an important factor of performance bottleneck and power consumption. One such effort is Computational Storage that moves the compute from the Host to the Device, and the Device only sends the computed result back to the Host at a much lower data rate.
Wolley proposes using NVMe over CXL (NVMeoC) to optimize the Host-Device data movement. In most applications, the Host only accesses a small portion of the entire block data retrieved from the Device. With NVMeoC, the Device keeps a CXL staging area that is managed as a part of the Host memory. Once the block data is moved to the CXL staging memory through NVMe operation, the actual Host-Device data movement using CXL.mem is just a fraction of the total block data. Wolley will compare in details of the latency and the power consumption between the NVMe over PCIe and NVMe over CXL in several different of applications.
Event Type
Exhibitor Forum
TimeWednesday, 15 November 20232:30pm - 3pm MST
Location503-504
Architecture and Networks
Data Movement and Memory
Hardware Technologies
TP
XO/EX