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Invited Talk: When Optimizing Software produces Optimized Hardware: A Case for Statically-Interpretable Control-Flow Programs
DescriptionNowadays, powerful optimizing compilers are needed to transform and specialize software for a particular machine, for performance and energy considerations. For example, compilers for High-level synthesis (HLS) can greatly facilitate the description of complex hardware implementations, by raising the level of abstraction to a classical imperative language such as C/C++, usually augmented with vendor-specific pragmas and APIs. Software is being used to describe hardware, but despite productivity improvements attaining high performance for the final designs remains a challenge: many crucial optimizations require substantial changes in control-flow structure, I/O approach, on-chip buffer management, function boundaries, exposing concurrency, etc.
In this talk, we discuss techniques and tools to assist with the development of optimized software, and optimized hardware using HLS. By specializing the compilation process to a specific class of programs, those whose control flow and dataflow can be exactly computed by means of interpretation at compile-time (e.g., many deep learning applications), we can for instance develop advanced code generation techniques for a class of sparse computation, powerful source-to-source transformations for better hardware designs via HLS, and verify the correctness of these optimized programs automatically.
In this talk, we discuss techniques and tools to assist with the development of optimized software, and optimized hardware using HLS. By specializing the compilation process to a specific class of programs, those whose control flow and dataflow can be exactly computed by means of interpretation at compile-time (e.g., many deep learning applications), we can for instance develop advanced code generation techniques for a class of sparse computation, powerful source-to-source transformations for better hardware designs via HLS, and verify the correctness of these optimized programs automatically.
Event Type
Workshop
TimeSunday, 12 November 20234:34pm - 4:58pm MST
Location704-706
Accelerators
Codesign
Heterogeneous Computing
Task Parallelism
W