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An Empirical Comparison of the RISC-V and AArch64 Instruction Sets
DescriptionIn this work we perform one of the first in-depth, empirical comparisons of the Arm and RISC-V instruction sets. We compare a series of benchmarks compiled with GCC 9.2 and 12.2, targeting the scalar subsets of Arm's Armv-8a and RISC-V's rv64g. We analyze instruction counts, critical paths and windowed critical paths to get an estimate of performance differences between the two instruction sets, determining where each has advantages and disadvantages. The results show the instruction sets are relatively closely matched on the metrics we evaluated for the benchmarks we considered, indicating that neither ISA has a large, inherent advantage over the other, architecturally.
Event Type
Workshop
TimeMonday, 13 November 20233:30pm - 3:50pm MST
Location507
Architecture and Networks
Hardware Technologies
W